The present invention relates generally to memories and, more specifically, to a method of setting all the memory locations in an array to a single logic value.
During certain parts of a memory operation, it is desirable that the contents of the memory be cleared. Depending upon the type of memory, it may include a clearing at the initialization stage of the operation and others may require clearing during the middle of an operation sequence. A cache memory is a type of memory which needs clearing or flushing at the initialization as well as during normal operating cycles. A cache memory is a small, high-speed memory which contains a copy of selected blocks of main memory. These blocks are chosen by an algorithm which attempts to predict which portions of main memory will be needed in the near future.
Cache memories consist of two major functional blocks. These are the cache data array and the tag store. The cache data array contains copies of various blocks of main memory, and is generally high speed, and located physically close to the CPU. The tag store is an associative memory which contains the high order address bits of the blocks of data in the cache data array. On each memory reference, the tag store control circuitry accesses the tag store to determine if the represented memory block is in the cache data array. If the block is in the cache data array, the system then takes the appropriate action, depending on the type of memory reference (read, write, invalidate, etc.).
One of the functions which must be performed on the tag store is called a flush. The flush sets the valid bit to .phi. (invalid) on all tag store locations. This is performed at power-up, and periodically during system operation. The flush assures that the control circuitry does not signal a false cache bit. It is also desireable, for testing purposes, to set all bits of the tag store to a known state during a flush operation.
Previously, the flush was accomplished by sequentially writing a .phi. (invalid) into all valid bit locations. Since this is a sequential operation, it required a hardware counter, and approximately 500 microseconds to flush a 1K deep tag store. Other improvements have divided the tag store into sections and clearing the sections one at a time. All of these prior art methods require excessive time to clear the tag store. Other require additional circuitry to produce the signals required to clear the tag store.